Field of the Invention
The present invention relates to a TFT active matrix substrate (hereinafter referred to as “TFT substrate”) in a liquid crystal display that employs the fringe field switching (FFS) mode in which liquid crystals are held between the TFT substrate including a thin film transistor (TFT) as a switching device and a counter substrate and to a method for manufacturing the TFT substrate.
Description of the Background Art
Generally, the display modes of liquid crystal displays are broadly divided into the twisted nematic (TN) mode and the transverse electric field mode typified by the in-plane switching (IPS) mode (IPS is a registered trademark) and the FFS mode. The liquid crystal displays in the transverse electric field mode have the feature of providing the wide viewing angle and the high contrast.
The IPS mode is a display mode in which displaying is performed by applying a transverse electric field onto the liquid crystals sandwiched between opposed substrates. The pixel electrodes and the common electrodes onto which the transverse electric field is applied are provided in the same layer. Thus, liquid crystal molecules positioned right above the pixel electrodes cannot be sufficiently driven, which reduces the transmittance.
In the FFS mode, meanwhile, the pixel electrodes and the common electrodes are disposed on the insulating film (planarization insulating film) that has been leveled, being opposed to one another via the interlayer insulating film. Thus, an oblique field (fringe field) is generated, allowing the transverse electric field to be applied onto the liquid crystal molecules including the ones right above the pixel electrodes, so that the liquid crystal molecules can be sufficiently driven. Therefore, the FFS mode provides a transmittance higher than that of the IPS mode.
In recent years, the liquid crystal displays are required to attain a higher aperture ratio and a further reduction in power consumption. Thus, the FFS-mode TFT substrate that includes a thick planarization insulating film is proposed in, for example, Japanese Patent Application Laid-Open No. 2009-128397, Japanese Patent Application Laid-Open No. 2009-133954, and Japanese Patent Application Laid-Open No. 2009-151285.
That is, in the FFS-mode TFT substrate described above, a thick planarization film is formed above the common wirings, the source wirings, and the TFT elements, whereby the parasitic capacitance of each signal line is reduced, which can suppress the power consumption. Moreover, the upper surface of the TFT substrate can be planarized by burying the steps caused by the respective wirings. This can eliminate the irregularities in the liquid crystal alignment that have been generated in the step portion, reducing the region that does not contribute to the displaying. The aperture ratio is thus improved. Furthermore, the pixel electrodes and the signal lines are disposed to be apart from each other, to thereby eliminate the effects of electric fields generated by the signal line. Thus, the pixel electrodes can be formed to overlap the signal lines. Consequently, the pixel electrodes are extended, whereby the pixel aperture ratio can be increased.
In the liquid crystal display including the FFS-mode TFT substrate, the liquid crystals are driven by the fringe field generated between the pixel electrodes (or the counter electrodes) that are provided in the upper layer and have slits and the counter electrodes (or the pixel electrodes) disposed in the layer below the pixel electrodes via the interlayer insulating film. In this configuration, the pixel electrodes and the counter electrodes are formed of a transparent conductive film based on an oxide such as indium tin oxide (ITO) containing indium oxide and tin oxide or InZnO containing indium oxide and zinc oxide, so that the pixel aperture ratio can be prevented from decreasing.
The pixel electrodes and the counter electrodes form the storage capacitance. Therefore, unlikely to the liquid crystal displays in the TN mode, the pattern of the storage capacitance does not need to be separately formed in the pixels. Thus, a high pixel aperture ratio can be provided.
In the switching device of the TFT substrate for the liquid crystal displays, amorphous silicon (Si) has been generally used as the channel layer of the semiconductor. The main reasons for this are as follows. Amorphous silicon, owing to its amorphousness, can be formed into a film having excellent uniformity of properties even on a large-area substrate. In addition, amorphous silicon can be formed into a film at a relatively low temperature. Thus, the film can be formed even on the low-priced glass substrate that has poor heat resistance. Therefore, amorphous silicon is well suited for the liquid crystal displays for use in the common televisions.
Meanwhile, in recent years, the development has been increasingly proceeding in the TFT elements including an oxide semiconductor as the channel layer. An amorphous-state film having excelling uniformity can be stably provided by optimizing the composition of the oxide semiconductor. Moreover, the oxide semiconductor has the mobility higher than that of the conventional amorphous silicon, thus being advantageous in providing small-sized and high-performance TFT elements. Therefore, the oxide semiconductor film is advantageous in providing a FFS-mode TFT substrate that has a higher pixel aperture ratio if the film is used in the TFT element of the FFS-mode TFT substrate that includes the planarization insulating film as described above.
As such an oxide semiconductor, the materials based on zinc oxide (ZnO) or the materials formed of zinc oxide containing gallium oxide (Ga2O3), indium oxide (In2O3), tin oxide (SnO2), and the like are mainly used. This technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-103957, Japanese Patent Application Laid-Open No. 2007-281409, and Kenji Nomura, et al., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, no. 432 (2004): 488-492.
In manufacturing the FFS structure including the above-mentioned planarization insulating film, a number of photolithography processes for forming patterns using a photomask are required. This leads to a problem of increasing manufacturing costs.
The formation of the TFT substrate including the TFT having a bottom-gate structure disclosed in, for example, Japanese Patent Application Laid-Open No. 2009-128397, Japanese Patent Application Laid-Open No. 2009-133954, and Japanese Patent Application Laid-Open No. 2009-151285 requires at least seven photography processes of: (1) patterning for forming a gate electrode; (2) patterning for forming a semiconductor layer; (3) patterning for forming a source electrode and a drain electrode; (4) forming a contact hole in a planarization insulating film; (5) patterning for forming a lower-layer electrode; (6) forming a contact hole in a protective insulating film; and (7) patterning for forming an upper-layer electrode.